What is IRQ, and What does it stand for? I am learning the 0-15 IRQ numbers and what the numbers are assigned to in school, but I have no idea what they are for, or what uses them. Why do I need to know these numbers?

That's the problem with those crappy A+ classes...

If you want to learn, do it on your own; don't expect the schools to be of any help.

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An IRQ is an Interupt Request. It asks to interupt what ever is going on to allow it to happen. Then the system returns to what ever it was doing. There is obviously a priority to the interupts. When you type on the keyboard, every key you hit produces an interupt to the system. The key stroke has to be serviced. As I remember the keyboard interupt is 9. The IRQ "points" to a location in low memory that contains the address of the Interupt Request Routine. This routine is what services the request and ends it.
All I/O is handeled by interupts. That is how the processor manages the keyboard while the disk is accessing while the screen is being painted while the internet port is receiving data. Otherwise some event would have to finish before anything else could occure.

Interrupts are generated and controlled by the Programmable Interrupt Controller (PIC) on the Motherboard.

Interrupts are being generated continuously in time with the on board clock, uselessly at a rate of one every 15 micro seconds.

When an interrupt occurs the CPU stops what it is doing and loads the address of the Interrupt Service Routine. This is usually a Jump Instruction that jumps to the code to service the interrupt. In the case of the keyboard, it will look into the keyboard buffer and process any characters it finds there.

If there is no device associated with an interrupt, the Interrupt Service routine will simple contain a return instruction.

Interrupt service routines are setup by the OS during the boot process and by drivers of particular devices.

Interrupts are prioritised with the lower interrupts having a higher priority. So if an lower level interrupt occurs while a higher level interrupt is still being processed it will be ignored. This is what is know as a maskable interrupt.

The is one other type on interrupt called a Non-maskable Interrupt (NMI). This is always executed whatever else is happening. On A PC there is only one NMI and this forces the CPU to run code in the BIOS that resets the machine. This is what happens when you press the reset key. It is connected directly to the NMI pin on the CPU.

Stuart

To correct a few things.

IRQ 0 through 15 are hardware interrupts, from the Interrupt controllers on the system board. There are also hardware interrupts like the NMI and hardware interrupts that can be generated by the processor, and software interrupts generated by programs.

Each hardware device uses an IRQ REQUEST line to the PIC to request service from the processor. For example, the keyboard/mouse controller on the system board generates one or more interrupts when a key is pressed and one or more when it is released. The disk drives generate one when a data transfer is complete.

The system timer generates an interrupt 18.2 times per second and is used to keep the clock updated and allow task swapping by the OS. There is also a programmable timer that Windows uses to schedule tasks and provide services that uses it own IRQ.

Under DOS, the IRQ's have a priority, 0 being the highest, then 1,8,9,10,11,12,14,15,3,4,5,6,7 (2 is used to cascade 8-15 in). This allows a higher priority interrupt to interrupt a lower one when it is being serviced. The older hardware designs and DOS did not allow much sharing of interrupts, so each device had to have its own IRQ assigned.

Under Windows, a rotating priority scheme is used and managed by Windows, so that one interrupt does not interrupt another one that is already being serviced. PnP hardware and Windows OS device drivers allow some IRQ's to be shared by different devices so there can be a lot more interrupting devices running under Windows. But IRQ priority has no real meaning under Windows, only the sequence that the pending interrupts are processed around the chain.