Hi, i got the following question and need some help. " Many computer architecture have string instructions which can operate on strings of considerable length and may take a relatively long time to execute. It would be UNSAFE to hold up all interrupts during the execution of these instructions, yet the general rule that tends to be followed wherever possible is that interrupts are permitted only between instructions, not in the middle. What Intel Pentium has done to solve this problem?" This is a question in my class, any i have no idea what the problem is. And why holding up all interrupts would be unsafe ? Any suggestions ?

Read the textbook? I'm not insensitive, I just don't care.

If i could find it in any text book, i wouldn't need to ask.

just guessing, since it's been like 2 or 3 years since college...but maybe even a wrong guess might get you thinking...*shrugs* lol anyway, i think holding all of the interrupts would be bad, since the instructions would take considerable time to execute (imagine a printer or some other device trying to signal for attention, or maybe another program running in the background had to abort) in college, we had to study the pentium, and design our own computers (adding new instructions, etc.) I somewhat remember how the pentium executes several instructions at the same time (it's like an assembly line, where in the 1st position, an instruction is being read, etc). If I remember correctly, when an interrupt would occur, the cpu would be reset so that it can start interpreting the interrupt. This isn't a problem, since the cpu keeps track of what instruction it was on (the pc counter or something...keeps track of the address). Thus, once the interrupt has been handled, it can go back from the last instruction it was working on.

Well, I have no idea how old that text book is. Nor do I know if my answer i'm gonna give is relevent to your quetion, But what I do know is that intel's relatively new Hyper Threading Technology allows a CPU to exucute two instructions in parallel with out disturbing one another. So, one physical processor is really two logical processors, its really cool. I have a P4 with HT and in Windows task manager I have two graphs one for each porcessor, I dont really have two CPUs, but my OS cant tell the differance between HT tech and a duel CPU plat-form. I multitask often and intels HT tech makes running two programs seem as if I was running them on two sepreate computers. I dont know if this is even close to what your talking about, but hey, if you dont know, now you do.

String instructions are a function of a high level language. There is no such thing as a string instruction as far as the CPU is concerned.

"...What Intel Pentium has done to solve this problem?" Basically, in out-of-order execution you also have a reorder buffer. The question doesn't tell you explicitly that the Pentium is OOE pipelined, but you better know that. An interrupt obviously stops the CPU's execution to handle another routine. While this is being done, the CPU state has to be saved. Remember, software expects the CPU to return results in the order they were sent. So, we have a specific problem when the CPU is tied for a short time. We have interrupts piling up in a buffer somewhere. Okay, why can't they wait? Some are precise interrupts - precise because to be completed they require a precise state of the CPU. Others are just errors, exceptions, kill signals, etc. What are we talking about with CPU state? Basically the state of the CPU's instruction queue is in a sequential order (relative to the program counter) and there is no mixing of executed and pending instructions. In other words, the order in which instructions were recieved is correlated to the order in which they have been processed. If we don't have this clean distinction, we will have problems finding where that interrupt should be put in the execution stream. If the CPU does have a clean order of instructions, then either the CPU knows how to go back and calculate where the buffered interrupt belongs in the chain of instructions or we get undefined behavior (which is always unsafe). Okay, so why can't these precise interrupts wait? Well, to the software the CPU executes instructions in order. In reality, it's picking and choosing (OOE). This is good, because it is generally more efficient. But, it complicates precise interrupt handling. The internal state of the CPU is not consistent with the order of instructions and hence the demands of precise interrupts. So, we use a reorder buffer. This buffer holds instructions and ensures the appropriate order of execution. The buffer logic is designed to allow CPU instructions to be executed in efficient order, but retains the sequence of in-order results. The CPU does its work while the buffer holds the necessary state information (the instruction stream order). Instructions are essentually inputted, sorted, and reordered.